Innovative Solutions for the emerging LAN/WAN & Broadband Markets
USB 2.0 PHY IP Cores
The following a representation of a complete USB 2.0 PHY Transceiver with all the optional IP Blocks fully integrated.
·Fully compliant with latest USB 2.0 specification.
· Fully Integrated HOST / DEVICE / OTG ( On-The-Go ) Transceiver when all optional features are included.
·Innovative technique for clock recovery from 480 Mbps data.
·High frequency PLL
·Advanced high-speed transmitter and receiver.
·Support High-Speed HS and Full-Speed FS modes (Also Low Speed LS with OHCI Interface in Host Mode)
·Implements UTMI and/or UTMI+ with optional features, both 8 bit and 16 bit Bi-Directional or Uni-Directional Data Bus.
· Integrated/Calibrated/Switchable 15K ohm Pull-down resistors on DP, DM for HOST.
· Integrated/Calibrated/Switchable 1.5K ohm Pull-Up resistors on DP, DM.
· Integrated/Calibrated Termination Resistors.
·Additional pin disconn (o) and SOF EOP Implementation for host UTMI in addition to USB 1.1 OHCI Interface
· Supports Host and Device Transceiver Implementations
· Optional Charge Pump for On-The-Go ( OTG ) Implementations
· Data Pulsing and VBus Pulsing Support for OTG SRP (Session Request Protocol) Support
· VBus Comparators for On-The-Go ( OTG ) Support
USB2.0 High-speed Serial Link at 480 Mbps and 12 Mbps for Host and Device Functionality.
Can be used in Host Controllers, Hub Applications and device functions where USB 2.0 Transceiver is required.
USB 2.0 HOST/DEVICE/ OTG Transceiver is a fully integrated PHY Core which is a super-set
of HOST and DEVICE PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceivers
integrated with On The Go Functionality and is compliant with the USB 2.0 Specification and
latest Revision of the On the Go and UTMI+ Specifications. It includes Data Pulsing, VBUS
Pulsing, VBUS Comparators for Session Detection to support HNP (Host Negotiation Protocol)
and SRP (Session Request Protocol), Clock/Data Recovery, on-chip PLL, Integrated & Calibrated
Termination and Pull-Up/Down Resistors with full Analog Transceiver functionality for the Complete USB 2.0 PHY.
USB 2 HOST / DEVICE / OTG transceiver has standard UTMI and UTMI+ (Version 1.0 Level 3) where needed so that ASIC vendors are isolated from the high speed and analog circuitry associated with the transceiver, thus reducing the design risk and
fastening the design cycle. The core's major blocks are clock data recovery for FS/HS, PLL, transceiver state machines, data encoder/decoder and High-Speed, Full-Speed/Low-Speed analog transceiver.
Copyright © 2003 by Soft Mixed Signal Corporation