SONET/SDH Transceiver PHY/PMD Products (OC-3, OC-12, OC-48)

• Innovative architecture to meet the SDH/ Sonet Jitter Spec utilizing deep sub-micron single poly CMOS process
• Fully integrated transceiver architectures that include: Clock synthesis, Clock Recovery, Wave shaping, low-jitter LVPECL interface, S/P/S functions.
• Fully in compliance with ANSI, Bellcore and ITU jitter Specifications
• Proven in multi-port end customer SOC designs
• Designed for multi- port applications using re-usable building blocks targeted for process migration/ new application domains
• Innovative (patent pending) CMOS architecture to guarantee compliance with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation
• High frequency PLLs with integrated on chip loop filters
• Proprietary Advanced Signal Processing techniques utilized for clock recovery provides on-chip filtering : immunity to external/PCB noise problem in existing solutions
• Supports 622.08 Mbit/s (OC-12) and 2.4Gbit/s (OC-48) with Selectable reference frequencies of 77.76 or 155.52 MHz
• LVPECL or LVDS circuitry for external interfacing to optical units
• Designed for multiple integration on a single IC for System-On-Chip applications
• Custom configurable width serializer-deserializer (SERDES) option

SMS OC-3 PHY Transceiver SMS2011.pdf

SMS OC-12 PHY Transceiver SMS2012.pdf

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